MOS semiconductor device

ABSTRACT

The semiconductor device according to an aspect of the present invention includes: a semiconductor substrate of a first conductive type; a first semiconductor layer of the first conductive type formed on the main surface of the semiconductor substrate, the impurity concentration of the first semiconductor layer being lower than that of the semiconductor substrate; a second and third semiconductor layers of a second conductive type formed on the first semiconductor layer, the second and third semiconductor layers being isolated from each other; a first and second MOS transistors MOS1 and MOS2 of the first conductive type formed in the second and third semiconductor layers, the first semiconductor layer and the semiconductor substrate serving as drains of the first and second MOS transistors; and a conductive layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2001-293928, filed on Sep. 26,2001, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor devices. In particular,the present invention relates to a semiconductor device including aplurality of MOS transistors, drains of which are commonly connected.

2. Related Background Art

As shown in FIG. 5, a lithium battery 30 typically is connected with aprotection circuit 40 for protecting the lithium battery 30 at the timeof charging/discharging. Generally, the protection circuit 40 includestwo MOS transistors MOS1 and MOS2, drains of which are commonlyconnected, diodes 41 and 42 connected in parallel to the respective MOStransistors, and a protection resistor 45, and is controlled by acontrol circuit 50 based on the potential across the lithium battery 30.

When the lithium battery 30 is discharged, a load 60 connected in serieswith the protection circuit 40 is disconnected from a battery charger70. In this state, the control circuit 50 controls the protectioncircuit 40 so that a potential at an “H” level is applied to gates G1and G2 of the MOS transistors MOS1 and MOS2, and after the potential ofthe lithium battery 30 becomes below a predetermined level, thepotential of the gate G2 of the MOS transistor MOS2 is lowered to an “L”level, as shown in FIG. 6(a). When the lithium battery 30 is charged,the load 60 is connected in parallel with the battery charger 70. Inthis state, the control circuit 50 controls the protection circuit 40 sothat a potential at the “H” level is applied to the gates G1 and G2 ofthe MOS transistors MOS1 and MOS2, and after the potential of thelithium battery 30 becomes below the predetermined level, the potentialof the gate G1 of the MOS transistor MOS1 is lowered to the “L” level.

The protection circuit 40 having the above-described structure is sealedwith mold resin on a common drain frame 85 to form a package 80, asshown in FIG. 7. Each of the MOS transistors MOS1 and MOS2 constitutingthe protection circuit 40 has a plurality of source terminals, as shownin FIG. 7. Generally, a package sealed with mold resin is thick.

Recently, as mobile devices including lithium batteries therein havebecome more compact, thinner, and lighter, it has been stronglyrequested that the size of MOS transistors be reduced. Under thecircumstances, CSPs (Chip Size Packages) have received attention asbeing the thinnest type of packages, which can replace rather-thickconventional packages sealed with mold resin.

As shown in FIG. 3, a CSP typically has such features that dicing is notperformed between two MOS transistors MOS1 and MOS2, and that solderballs 18 serving as electrodes are formed on the chip, which areconnected to a gate G1 and sources S1 of the MOS transistor MOS1, and agate G2 and sources S2 of the MOS transistor MOS2. CSPs having such astructure are expected to become the mainstream semiconductor devicesfor lithium battery protection circuits, since the height of such CSPsis considerably reduced as compared with conventional devices.

FIG. 4 shows a section view of a semiconductor device having theabove-described CSP structure, taken along line A-A′ of FIG. 3. Thissemiconductor device has a plurality of N-channel MOS transistors havinga trench gate structure. In this semiconductor device, an N⁻ epitaxiallayer 4 having a high resistance is formed on an N⁺ semiconductorsubstrate 2 serving as a drain; a P-type semiconductor layer 6 servingas a base is formed on the N⁻ epitaxial layer 4; and a plurality ofN-channel MOS transistors are formed in the P-type semiconductor layer6. The structure of such MOS transistors will be described in detailwith reference to FIG. 2, which is an enlarged view of the MOStransistors shown in FIG. 4.

As shown in FIG. 2, N⁺ semiconductor regions 8, and P⁺ semiconductorregions 10 for applying a predetermined potential to the P-typesemiconductor layer 6 are formed near the surface of the P-typesemiconductor layer 6. A P⁺ semiconductor region 10 is formed near thesurface of the P-type semiconductor layer 6 between two N⁺ semiconductorregions 8 so as to contact the N⁺ semiconductor regions 8. Further, theP-type semiconductor layer 6 includes trenches reaching the N⁻ epitaxiallayer 4, in which gate electrodes 12 are formed via insulating films 14,which are gate insulating films. An insulating film 16 is formed tocover each gate electrode 12. The insulating film 16 does not completelycover the N⁺ semiconductor regions 8 serving as sources, but exposespart of the surface of the sources 8. A metal layer 17 is formed tocover the main surface of the substrate thus constituted. Apredetermined potential is applied to the P-type semiconductor layer 6and the N⁺ semiconductor regions 8 via the metal layer 17.

When a predetermined potential is applied to the gate electrodes 12,electrons flow from the N⁺ semiconductor regions 8 serving as thesources to the N⁺ semiconductor substrate 2 serving as the drain, viathe P-type semiconductor layer 6 serving as the base and the N⁻epitaxial layer 4, as shown in FIG. 4.

The MOS transistors MOS1 and MOS2 are isolated by an element isolationfilm 19, as shown in FIG. 4.

However, since the drain does not serve as an electrode in thisCSP-structure semiconductor device as show in FIGS. 3 and 4, a currentI_(S1S2) flows through the interface between the epitaxial layer 4 andthe silicon semiconductor substrate 2, in the traverse direction fromthe transistor MOS1 side to the transistor MOS2 side. The reason forthis is that although the resistivity of the silicon substrate 2 isabout 3 mΩ·cm, which is a few hundred times lower than that of theepitaxial layer 4, the section area of the current path is small, andthe traverse length of the chip is 1 mm or more, resulting in that theresistance value of the silicon substrate is increased. Due to such afeature, there is a problem in that ON resistance of this device isincreased as compared with the case where a current flows in thevertical direction through each of the transistors MOS1 and MOS2 havingthe trench gate structure.

SUMMARY OF THE INVENTION

According to an embodiment of the present invention, a semiconductordevice includes: a semiconductor substrate of a first conductive type; afirst semiconductor layer of the first conductive type formed on a mainsurface of the semiconductor substrate, the impurity concentration ofthe first semiconductor layer being lower than that of the semiconductorsubstrate; a second and third semiconductor layers of a secondconductive type formed on the first semiconductor layer, the second andthird semiconductor layers being isolated from each other; a first MOStransistor of the first conductive type formed in the secondsemiconductor layer, the first semiconductor layer and the semiconductorsubstrate serving as drains of the first MOS transistor; a second MOStransistor of the first conductive type formed in the thirdsemiconductor layer, the first semiconductor layer and the semiconductorsubstrate serving as drains of the second MOS transistor; and aconductive layer formed on a reverse surface of the semiconductorsubstrate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a section view showing the structure of a semiconductor deviceaccording to an embodiment of the present invention.

FIG. 2 is a section view showing the structure of a MOS transistorhaving a trench gate structure.

FIG. 3 is a top view of a CSP-structure semiconductor device.

FIG. 4 is a section view showing the structure of a conventionalsemiconductor device.

FIG. 5 is a circuit diagram showing the structure of a lithium batteryprotection circuit.

FIGS. 6(a) and 6(b) show waveforms of signals applied to gates of MOStransistors constituting a lithium battery protection circuit.

FIG. 7 is a diagram showing a package of a lithium battery protectioncircuit.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1 shows the structure of a semiconductor device according to anembodiment of the present invention. The semiconductor device of thisembodiment is obtained by forming a conductive layer 20 having a lowresistance on the reverse side, i.e., the side opposite to the side onwhich the MOS transistors are formed, of the semiconductor substrate 2of the conventional semiconductor device shown in FIGS. 3 and 4.

That is, in the semiconductor device of this embodiment, an N⁻ epitaxiallayer 4 having a high resistance is formed on an N⁺ semiconductorsubstrate 2 serving as a drain; a P-type semiconductor layer 6 servingas a base is formed on the N⁻ epitaxial layer 4; and a plurality ofN-channel MOS transistors (two in the drawing) having a trench gatestructure are formed in the P-type semiconductor layer 6. The structureof the MOS transistors MOS1 and MOS2 will be described in detail belowwith reference to FIG. 2, which is an enlarged view of the MOStransistor shown in FIG. 1.

As shown in FIG. 2, N⁺ semiconductor regions 8, and P⁺ semiconductorregions 10 for applying a predetermined potential to the P-typesemiconductor layer 6 are formed near the surface of the P-typesemiconductor layer 6. A P⁺ semiconductor region 10 is formed near thesurface of the P-type semiconductor layer 6 between two N⁺ semiconductorregions 8 so as to contact the N⁺ semiconductor regions 8. Further, theP-type semiconductor layer 6 includes trenches reaching the N⁻ epitaxiallayer 4, in which gate electrodes 12 are formed via insulating films 14,which are gate insulating films. An insulating film 16 is formed tocover each gate electrode 12. The insulating film 16 does not completelycover the N⁺ semiconductor regions 8 serving as sources, but exposespart of the surface of the sources 8. A metal layer 17 is formed tocover the main surface of the substrate thus constituted. Apredetermined potential is applied to the P-type semiconductor layer 6and the N⁺ semiconductor regions 8 via the metal layer 17. The MOStransistors MOS1 and MOS2 are isolated by an element isolation film 19,as shown in FIG. 1. Accordingly, the metal layer 17 on the MOStransistors MOS1 and MOS2 is discontinued over the element isolationfilm 19. Solder balls 18 for drawing source electrodes are formed on themetal layer 17. In addition, as in the case of the conventional deviceshown in FIG. 3, the gate electrodes 12 of the MOS transistors MOS1 andMOS2 are commonly connected with the solder balls G1 and G2,respectively.

When a predetermined potential is applied to the gate electrodes 12 ofthe MOS transistors MOS1 and MOS2 via the solder balls G1 and G2,carriers move from the N⁺ semiconductor regions 8 serving as sources ofthe transistor MOS1 to the MOS transistor MOS2 via the P-typesemiconductor layer 6 serving as the base, the N⁻ epitaxial layer 4, theN⁺ semiconductor substrate 2 serving as the drain, and the conductivelayer 20.

A low-resistance metal having a thickness of a few mm is used as theconductive layer 20. Typical materials of the conductive layer 20 are,vanadium-nickel-gold (V—Ni—Au), aluminum, etc. It is preferable that theconductive layer 20 is formed before the solder balls 18 are formed.

As shown in FIG. 1, in this embodiment, around the connection point ofthe transistors MOS1 and MOS2, a current flows through the interfacebetween the epitaxial layer 4 and the semiconductor substrate 2 in thetraverse direction from the MOS1 side to the MOS2 side, as in the caseof the conventional device. However, in other portions, a current flowsin the vertical direction toward the drain at the lower side because ofthe existence of a low-resistance conductive layer (metal layer) 20.This change in current path is determined by the difference inresistance value between the case where the current flows horizontallyand the case where the current flows vertically. The current flowsthrough the path with which the resistance value is smaller.

Since the resistance value in the conductive layer 20 is substantiallyzero, the current having reached the conductive layer 20 horizontallyflows toward the portion below the transistor MOS2 without loss, andthen vertically flows toward the sources of the transistor MOS2.

In this embodiment, since the current flows in the above-describedmanner, the ON resistance is substantially the same as that in the casewhere a current passes vertically through each of the transistors MOS1and MOS2. Accordingly, the problem in the conventional devices that theON resistance is increased can be solved in the present invention.Further, since the present invention is a semiconductor device havingthe CSP structure, it is possible to reduce the thickness.

Thus, in a semiconductor device having the CSP structure with two MOStransistors, it is possible to change the current path from thehorizontal direction around the interface of the semiconductor substrate2 to the vertical direction by forming a low-resistance metal layer 20in the drain side, which is not used as an electrode. In this way, it ispossible to reduce the ON resistance, thereby achieving theON-resistance substantially identical to the ON resistance in the casewhere each of the two MOS transistors is independently operated.

Although N-channel MOS transistors (MOSFETS) having a trench gatestructure are used in this embodiment, the present invention can beapplied to P-channel MOSFETs having the opposite polarity. Further, thepresent invention can be applied to planar MOSFETs, having a differentstructure. In addition, although the present invention has beendescribed taking the case where a current flows from the sources S1 ofthe MOS transistor MOS1 to the sources S2 of the MOS transistor MOS2 asan example, the same advantageous effects can be obtained if the currentflows in the opposite direction.

As described above, according to the present invention, it is possibleto prevent the increase in ON-resistance, and to fabricate asemiconductor device whose package is thinner.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcepts as defined by the appended claims and their equivalents.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate of a first conductive type; a firstsemiconductor layer of the first conductive type formed on a mainsurface of said semiconductor substrate, an impurity concentration ofsaid first semiconductor layer being lower than that of saidsemiconductor substrate; second and third semiconductor layers of asecond conductive type formed on said first semiconductor layer; a firstMOS transistor of the first conductive type including first sourceregions formed in said second semiconductor layer, said firstsemiconductor layer and said semiconductor substrate serving as drainsof said first MOS transistor; a first metal layer electrically connectedto said first source regions a second MOS transistor of the firstconductive type including second source regions; formed in said thirdsemiconductor layer, said first semiconductor layer and saidsemiconductor substrate serving as drains of said second MOS transistor;a second metal layer electrically connected to said second sourceregions, said second metal layer being isolated from said first metallayer; and a conductive layer formed on a reverse surface of saidsemiconductor substrate; wherein the conductive layer forms a currentflow path from the first MOS transistor to the second MOS transistor. 2.The semiconductor device according to claim 1, wherein: said first MOStransistor includes a gate electrode formed, via a gate insulating film,in a trench formed in said second semiconductor layer so as to reachsaid first semiconductor layer, and said first source regions providednear a surface of said second semiconductor layer at both sides of saidtrench, said first source regions contacting said trench; and saidsecond MOS transistor includes a gate electrode formed, via a gateinsulating film, in a trench formed in said third semiconductor layer soas to reach said first semiconductor layer, and said second sourceregions provided near a surface of said third semiconductor layer atboth sides of said trench, said second source regions contacting saidtrench.
 3. The semiconductor device according to claim 2, wherein: eachof said first and second MOS transistors includes a plurality of saidgate electrodes and a respective plurality of said first and secondsource regions; said first and second source regions of said first andsecond MOS transistors are covered by respective first and second metallayers; and solder balls for drawing source electrodes are formed oneach of the common metal layers.
 4. The semiconductor device accordingto claim 3, wherein said gate electrodes of each of said first andsecond MOS transistors transistor are commonly connected to each otherand said gate electrodes of said second MOS transistor are commonlyconnected to each other.
 5. The semiconductor device according to claim3, further comprising: a fourth semiconductor layer of the secondconductive type, provided near a surface of said second semiconductorlayer between adjacent gate electrodes of said first MOS transistor andbetween said first source regions corresponding to the adjacent gateelectrodes, an impurity concentration of said fourth semiconductor layerbeing higher than that of said second semiconductor layer; and a fifthsemiconductor layer of the second conductive type, provided near asurface of said third semiconductor layer between adjacent gateelectrodes of said second MOS transistor and between said second sourceregions corresponding to the adjacent gate electrodes, impurityconcentration of said fifth semiconductor layer being higher than thatof said third semiconductor layer.
 6. The semiconductor device accordingto claim 5, wherein said fourth and fifth semiconductor layers arecovered by said respective first and second metal layers.
 7. Thesemiconductor device according to claim 1, wherein said firstsemiconductor layer is an epitaxial layer.
 8. The semiconductor deviceaccording to claim 1, wherein said conductive layer is formed of avanadium-nickel-gold alloy or aluminum.
 9. The semiconductor deviceaccording to claim 2, wherein the gate electrode of the first MOStransistor is electrically isolated from the gate electrode of thesecond MOS transistor.
 10. The semiconductor device according to claim1, wherein said first metal layer is over a gate electrode of the firstMOS transistor and spaced from the gate electrode of the first MOStransistor by an insulating film.
 11. The semiconductor device accordingto claim 2, wherein the gate electrode of said first MOS transistorextends inwardly of said second semiconductor layer, and the gateelectrode of said second MOS transistor extends inwardly of the saidthird semiconductor layer.
 12. The semiconductor device according toclaim 11, wherein the gate electrode of said first MOS transistorextends through said second semiconductor layer, and the gate electrodeof said second MOS transistor extends through the third semiconductorlayer.
 13. The semiconductor device according to claim 1, wherein thefirst conductive type is n type.
 14. The semiconductor device accordingto claim 10, further comprising a first insulating layer overlying thegate electrode of the first MOS transistor and a portion of the firstsource regions, wherein said first conductive metal layer is isolatedfrom the gate electrode of the first MOS transistor by the firstinsulating layer, and contacts the first source regions in a locationadjacent to the first insulating layer.
 15. The semiconductor deviceaccording to claim 14, further comprising a second insulating layerlocated over the second semiconductor layer and the third semiconductorlayer, wherein the first conductive metal layer and the secondconductive metal layers are separated from one another by the secondinsulating layer.
 16. The semiconductor device according to claim 1,wherein said second semiconductor layer extends from the first MOStransistor to the second MOS transistor.
 17. A semiconductor devicecomprising: a semiconductor substrate of a first conductive type havinga main surface and a reverse surface; a first semiconductor layer of thefirst conductive type formed on the main surface of said semiconductorsubstrate, an impurity concentration of said first semiconductor layerbeing lower than that of said semiconductor substrate; second and thirdsemiconductor layers of a second conductive type formed on said firstsemiconductor layer; a first MOS transistor of the first conductive typeincluding first source regions formed in said second semiconductorlayer, said first semiconductor layer and said semiconductor substrateserving as drains of said first MOS transistor; a first metal layerelectrically connected to said first source regions a second MOStransistor of the first conductive type including second source regionsformed in said third semiconductor layer, said first semiconductor layerand said semiconductor substrate serving as drains of said second MOStransistor, said second and third semiconductor layers being adjacent toeach other on the first semiconductor layer; a second metal layerelectrically connected to said second source regions, said second metallayer being isolated from said first metal layer; and a conductive layerformed on the reverse surface of said semiconductor substrate.
 18. Thesemiconductor device of claim 17, wherein the conductive layer forms acurrent flow path from the first MOS transistor to the second MOStransistor.
 19. The semiconductor device of claim 18, said first MOStransistor includes a gate electrode formed, via a gate insulating film,in a trench formed in said second semiconductor layer so as to reachsaid first semiconductor layer, and said first source regions areprovided near a surface of said second semiconductor layer at both sidesof said trench, said first source regions contacting said trench; andsaid second MOS transistor includes a gate electrode formed, via a gateinsulating film, in a trench formed in said third semiconductor layer soas to reach said first semiconductor layer, and said second sourceregions are provided near a surface of said third semiconductor layer atboth sides of said trench, said second source regions contacting saidtrench.
 20. The semiconductor device of claim 19, wherein the firstmetal layer overlies the gate electrode of the first MOS transistor andis separated from the gate electrode of the first MOS transistor by aninsulating film.